Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. An FPGA may also include various dedicated logic circuits, such as memories, microprocessors, digital clock managers (DCMs), and input/output (I/O) transceivers.
To implement a circuit design using one or more FPGAs disposed on a circuit board, a logic designer produces a functional description of the circuit design using a suitable hardware description language (HDL), such as the Very high-speed integrated circuit Hardware Description Language (VHDL) and VERILOG. The HDL code is then synthesized to produce a logical representation of the circuit design. The physical implementation of the circuit design is realized by placing and routing the synthesized circuit design in the FPGA(s) using the programmable logic blocks and programmable logic fabric. The place and route phases of implementing a circuit design involve generating a layout of the circuit elements on the FPGA(s) and defining the signal lines (routing resources) that connect the elements. Typically, the place and route phase is iterated until the design meets timing constraints established by the logic designer.
When the designer achieves timing closure in the place and route phase, schematics are produced with a particular pin configuration. If no attention has been paid to circuit board level routing requirements, the selected pin configuration can increase costs. For example, the selected pin configuration may increase the number of layers in the circuit board to route the signals or the problem may not be solvable manually by a layout designer in a reasonable period of time. The problem is further magnified when there are multiple FPGAs on the circuit board. Conventionally, the process of pin assignment and placement and layout of the devices on the circuit board is handled by back and forth discussions between the design team and the circuit board layout team. Depending on the complexity and pin count, closing this loop may take many weeks.
Accordingly, there exists a need in the art for an improved method and apparatus for implementing a circuit design for integrated circuitry on a circuit board.